The following publications are possibly variants of this publication:
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- A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked LoopJinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang. jssc, 45(5):1036-1047, 2010. [doi]
- A Fast-Lock Low-Power Subranging Digital Delay-Locked LoopHsin-Shu Chen, Jyun-Cheng Lin. ieicet, 93-C(6):855-860, 2010. [doi]