Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS - researchr publication

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Kairang Chen, Martin Nielsen-Lonn, Atila Alvandpour. Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS. In IEEE Nordic Circuits and Systems Conference, NORCAS 2016, Copenhagen, Denmark, November 1-2, 2016. pages 1-4, IEEE, 2016. [doi]

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