Table of Contents

• Area-efficiency trade-offs in integrated switched-capacitor DC-DC convertersFrederik Monrad Spliid, Dennis Oland Larsen, Arnold Knott. 1-5 [doi]
• Data type dependent energy consumption estimationPriit Ruberg, Keijo Lass, Peeter Ellervee. 1-5 [doi]
• Bivariate function approximation with encoded gradientsJochen Rust, Steffen Paul. 1-6 [doi]
• A current-mode analog-to-time converter with short-pulse output capability using local intra-cell activation for high-speed time-domain biosensor arrayKei Ikeda, Atsuki Kobayashi, Kazuo Nakazato, Kiichi Niitsu. 1-6 [doi]
• IoT-based fall detection system with energy efficient sensor nodesTuan Nguyen Gia, Igor Tcarenko, Victor K. Sarker, Amir M. Rahmani, Tomi Westerlund, Pasi Liljeberg, Hannu Tenhunen. 1-6 [doi]
• Exclusive control for compound operations on hardware transactional memoryKeisuke Mashita, Anju Hirota, Tomoaki Tsumura. 1-6 [doi]
• A 10 MHz bandwidth continuous-time delta-sigma modulator for portable ultrasound scannersPere Llimos Muntal, Ivan H. H. Jørgensen, Erik Bruun. 1-5 [doi]
• A 2 GHz low noise amplifier with transformer input matching in 28 nm CMOSRobert Kostack, Christoph Tzschoppe, Herbert Stockinger, Udo Jorges, Frank Ellinger. 1-6 [doi]
• Multiphase digitally controlled oscillator for future 5G phased arrays in 90 nm CMOSArnout Devos, Marco Vigilante, Patrick Reynaert. 1-4 [doi]
• Energy proportional computing with OpenCL on a FPGA-based overlay architectureAwais Hussain Sani, Jose Luis Nunez-Yanez. 1-6 [doi]
• Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizingAli Asghar Vatanjou, Even Låte, Trond Ytterdal, Snorre Aunet. 1-4 [doi]
• A fully-synthesized TRNG with lightweight cellular-automata based post-processing stage in 130nm CMOSJuan Cartagena, Hector Gomez, Elkim Roa. 1-5 [doi]
• A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 230 mV start-up voltageT. Lee, H. R. B. Kennedy, Rares Bodnar, William Redman-White. 1-4 [doi]
• 13-Bit RF-DAC up to 14GS/s at 3.5 GHz introducing Smart-SwitchingLukas Frager, Oner Hanay, Erkan Bayram, Renato Negra. 1-4 [doi]
• Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aidsYoni Yosef-Hay, Pere Llimos Muntal, Dennis Oland Larsen, Ivan H. H. Jørgensen. 1-5 [doi]
• Oscillation ring testing methodology of TSVs in 3D stacked ICsShadi M. Harb, William R. Eisenstadt. 1-4 [doi]
• High-level NoC model for MPSoC compilersChristian Menard, Andres Goens, Jerónimo Castrillón. 1-6 [doi]
• Current-steering DAC linearisation by impedance transformationStefan Muller, Oner Hanay, Renato Negra. 1-4 [doi]
• Distributed systemc simulation on manycore serversJanne Virtanen, Panu Sjovall, Marko Viitanen, Timo D. Hämäläinen, Jarno Vanne. 1-6 [doi]
• CPCIe: A compression-enabled PCIe core for energy and performance optimizationMohd Amiruddin Zainol, Jose Luis Nunez-Yanez. 1-6 [doi]
• A special processor design for Nucleotide Basic Local Alignment Search Tool with a new Banded two-hit methodChih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen, Xiao-Xuan Huang, Yi-Chang Lu. 1-5 [doi]
• Performance evaluation of classical differential rectifier by using forward body biasing techniqueShailesh Singh Chouhan, Kari Halonen. 1-4 [doi]
• Current driver with read-out HV protection for neural stimulationDmitry Osipov, Steffen Paul, Serge Strokov, Andreas K. Kreiter, Andreas Schander, Tobias Teßmann, Walter Lang. 1-4 [doi]
• A database accelerator for energy-efficient query processing and optimizationSebastian Haas, Oliver Arnold, Stefan Scholze, Sebastian Höppner, Georg Ellguth, Andreas Dixius, Annett Ungethüm, Eric Mier, Benedikt Noethen, Emil Matús, Stefan Schiefer, Love Cederstroem, Fabian Pilz, Christian Mayr, René Schüffny, Wolfgang Lehner, Gerhard P. Fettweis. 1-5 [doi]
• 2 frequency multiplier based on DLL with output frequency from 4 to 6 GHzErkan Bayram, Oner Hanay, Renato Negra. 1-4 [doi]
• Hierarchical design of a low power standing wave oscillator based clock distribution networkWei Zhang, Youde Hu, Yuxiang Huan, Zhuo Zou, Keji Cui, Dongxuan Bao, Dashan Pan, Lebo Wang, Li-Rong Zheng. 1-5 [doi]
• Natural logarithm and division floating-point high throughput co-processor implemented in FPGAPeter Malík. 1-6 [doi]
• 20-300 MHz frequency generator with -70 dBc reference spur for low jitter serial applicationsGürkan Yilmaz, Catherine Dehollain. 1-4 [doi]
• Sensor data fusion with MPSoCSim in the context of electric vehicle charging stationsIvan Stoychev, Philipp Wehner, Jens Rettkowski, Tobias Kalb, Diana Göhringer, Jürgen Oehm. 1-6 [doi]
• A wideband blocker-resilient RF front-end with selective input-impedance matching for direct-ΔΣ-receiver architecturesFaizan Ul Haq, Mikko Englund, Kari Stadius, Marko Kosunen, Jussi Ryynänen, Kimmo Koli, Kim B. Ostman. 1-4 [doi]
• Solar panel modelling for low illuminance indoor conditionsXinyu Ma, Sebastian Bader, Bengt Oelmann. 1-6 [doi]
• Design of a VCO-based ADC in 28 nm CMOSVishnu Unnikrishnan, Mark Vesterbacka. 1-4 [doi]
• Area and power consumption trade-off for Σ-Δ decimation filter in mixed signal wearable ICAlessandro Palla, Gabriele Meoni, Luca Fanucci. 1-5 [doi]
• Fully integrated triple-mode sigma-delta modulator for speech codecLei Zou, Marco De Blasi, Gino Rocca, Marco Grassi, Piero Malcovati, Andrea Baschirotto. 1-4 [doi]
• A CMOS 16k microelectrode array as docking platform for autonomous microsystemsLukas Straczek, Thomas Maeke, Dominic A. Funke, Abhishek Sharma, John S. McCaskill, Jürgen Oehm. 1-6 [doi]
• An experimental comparison between two widely adopted phase noise modelsFederico Pepe, Pietro Andreani. 1-4 [doi]
• Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOSKairang Chen, Martin Nielsen-Lonn, Atila Alvandpour. 1-4 [doi]
• The REPLICA on-chip networkMartti Forsell, Jussi Roivainen, Ville Leppänen. 1-6 [doi]
• Voltage multiplier arrangement for heavy load conditions in RF energy harvestingShailesh Singh Chouhan, Kari Halonen. 1-5 [doi]
• Accelerating MPSoC design space exploration within system-level frameworksSyed Abbas Ali Shah, Bastian Farkas, Rolf Meyer, Mladen Berekovic. 1-6 [doi]
• A novel random approach to diagnostic test generationEmmanuel Ovie Osimiry, Raimund Ubar, Sergei Kostin, Jaan Raik. 1-4 [doi]
• Design and simulation of a quaternary memory cell based on a physical memristorJonathan Taylor, Alberto Nannarelli. 1-6 [doi]
• Using OpenCL to rapidly prototype FPGA designsKui Wang, Jari Nurmi. 1-6 [doi]
• Dynamically reconfigurable real-time hardware architecture for channel utilisation analysis in industrial wireless communicationLudwig Karsthof, Mingjie Hao, Jochen Rust, Dimitri Block, Uwe Meier, Steffen Paul. 1-6 [doi]
• A 1.3-μW 12-bit incremental ΔΣ ADC for energy harvesting sensor applicationsShiva Jamali-Zavareh, Jarno Salomaa, Mika Pulkkinen, Shailesh Singh Chouhan, Kari Halonen. 1-4 [doi]
• Automatic generation of RTL connectivity checkers from SystemC TLM and IP-XACT descriptionsTomas Grimm, Djones Lettnin, Michael Hübner. 1-6 [doi]
• DRAM row-hammer attack reduction using dummy cellsHector Gomez, Andres Amaya, Elkim Roa. 1-4 [doi]
• An OR-type cascaded match line scheme for high-performance and EDP-efficient ternary content addressable memoryJianwei Zhang, Shanxing Zheng, Fei Teng, Qiuhong Ding, Xiaoming Chen. 1-6 [doi]
• FPGA implementation and integration of a reconfigurable CAN-based co-processor to the coffee risc processorFarid Shamani, Vida Fakour Sevom, Tapani Ahonen, Jari Nurmi. 1-6 [doi]
• True random number generation from bang-bang ADPLL jitterFelix Neumarker, Sebastian Höppner, Andreas Dixius, Christian Mayr. 1-5 [doi]
• Optimizing simulation times in biomedical systems containing Quasi-Infinite ResistorsSaam Iranmanesh, Majd Eid, Esther Rodríguez-Villegas. 1-4 [doi]
• OpenCL programmable exposed datapath high performance low-power image signal processorJoonas Multanen, Heikki Kultala, Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala, Aram Danielyan, Cristovao Cruz. 1-6 [doi]