A 40Gb/s TX and RX chip set in 65nm CMOS

Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee. A 40Gb/s TX and RX chip set in 65nm CMOS. In IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011. pages 146-148, IEEE, 2011. [doi]

@inproceedings{ChenSLHL11,
  title = {A 40Gb/s TX and RX chip set in 65nm CMOS},
  author = {Ming-Shuan Chen and Yu-Nan Shih and Chen-Lun Lin and Hao-Wei Hung and Jri Lee},
  year = {2011},
  doi = {10.1109/ISSCC.2011.5746257},
  url = {http://dx.doi.org/10.1109/ISSCC.2011.5746257},
  researchr = {https://researchr.org/publication/ChenSLHL11},
  cites = {0},
  citedby = {0},
  pages = {146-148},
  booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011},
  publisher = {IEEE},
  isbn = {978-1-61284-303-2},
}