Low-power LDPC decoder design exploiting memory error statistics

JunLin Chen, Lei Wang. Low-power LDPC decoder design exploiting memory error statistics. In 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, Amherst, MA, USA, October 12-14, 2015. pages 171-176, IEEE, 2015. [doi]

Abstract

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