On Retiming for FPGA Logic Module Minimization - researchr publication authors

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Yao-Ping Chen, D. F. Wong. On Retiming for FPGA Logic Module Minimization. In Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD 94, Cambridge, MA, USA, October 10-12, 1994. pages 394-397, IEEE Computer Society, 1994.

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