Improving system latency of AI accelerator with on-chip pipelined activation preprocessing and multi-mode batch inference - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Wenxuan Chen, Zheng Wang, Ming Lei, Bo Dong, Zhuo Wang, Yongkui Yang, Chao Chen 0022, Weiyu Guo, Chen Liang, Qian Zhang, Wenqi Fang, Zhibin Yu. Improving system latency of AI accelerator with on-chip pipelined activation preprocessing and multi-mode batch inference. In 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021, Washington, DC, USA, June 6-9, 2021. pages 1-4, IEEE, 2021. [doi]

This author has not been identified. Look up 'Wenxuan Chen' in GoogleThis author has not been identified. Look up 'Zheng Wang' in GoogleThis author has not been identified. Look up 'Ming Lei' in GoogleThis author has not been identified. Look up 'Bo Dong' in GoogleThis author has not been identified. Look up 'Zhuo Wang' in GoogleThis author has not been identified. Look up 'Yongkui Yang' in GoogleThis author has not been identified. Look up 'Chao Chen 0022' in GoogleThis author has not been identified. Look up 'Weiyu Guo' in GoogleThis author has not been identified. Look up 'Chen Liang' in GoogleThis author has not been identified. Look up 'Qian Zhang' in GoogleThis author has not been identified. Look up 'Wenqi Fang' in GoogleThis author has not been identified. Look up 'Zhibin Yu' in Google

runs on WebDSL