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A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS

Mingliang Chen, Keke Wu, Yupeng Shen, Zhiyu Wang, Hua Chen 0003, Jiarui Liu, Faxin Yu. A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS. IEICE Electronic Express, 18(11):20210171, 2021. [doi]

Authors

Mingliang Chen

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Keke Wu

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Yupeng Shen

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Zhiyu Wang

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Hua Chen 0003

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Jiarui Liu

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Faxin Yu

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