The following publications are possibly variants of this publication:
- Width and Timing-Constrained Wire Sizing for Critical Area MinimizationJin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang. apccas 2006: 1276-1279 [doi]
- Zero skew clock-tree optimization with buffer insertion/sizing and wire sizingJeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen. tcad, 23(4):565-572, 2004. [doi]
- Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian RelaxationYu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong. vlsi, 2002(3):587-594, 2002. [doi]
- Timing-constrained yield-driven wire sizing for critical area minimizationJin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee. iscas 2006: [doi]