Utilization of multi-bit flip-flops for clock power reduction

Zhi-Wei Chen, Jin-Tai Yan. Utilization of multi-bit flip-flops for clock power reduction. In 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012. pages 677-680, IEEE, 2012. [doi]

@inproceedings{ChenY12-24,
  title = {Utilization of multi-bit flip-flops for clock power reduction},
  author = {Zhi-Wei Chen and Jin-Tai Yan},
  year = {2012},
  doi = {10.1109/ICECS.2012.6463635},
  url = {http://dx.doi.org/10.1109/ICECS.2012.6463635},
  researchr = {https://researchr.org/publication/ChenY12-24},
  cites = {0},
  citedby = {0},
  pages = {677-680},
  booktitle = {19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012},
  publisher = {IEEE},
  isbn = {978-1-4673-1259-2},
}