The following publications are possibly variants of this publication:
- Routability-constrained multi-bit flip-flop construction for clock power reductionZhi-Wei Chen, Jin-Tai Yan. integration, 46(3):290-300, 2013. [doi]
- Routability-driven flip-flop merging process for clock power reductionZhi-Wei Chen, Jin-Tai Yan. iccd 2010: 203-208 [doi]
- INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphsIris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang, Evan Y.-W. Tsai, Lancer S.-F. Chen. ispd 2011: 115-122 [doi]
- In-placement clock-tree aware multi-bit flip-flop generation for power optimizationChih-Cheng Hsu, Yu-chuan Chen, Mark Po-Hung Lin. iccad 2013: 592-598 [doi]