Zhi-Wei Chen, Jin-Tai Yan. Timing-constrained replacement using spare cells for design changes. In José Luis Ayala, Alex K. Jones, Patrick H. Madden, Ayse Kivilcim Coskun, editors, Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013. pages 347-348, ACM, 2013. [doi]
@inproceedings{ChenY13-1,
title = {Timing-constrained replacement using spare cells for design changes},
author = {Zhi-Wei Chen and Jin-Tai Yan},
year = {2013},
doi = {10.1145/2483028.2483136},
url = {http://doi.acm.org/10.1145/2483028.2483136},
researchr = {https://researchr.org/publication/ChenY13-1},
cites = {0},
citedby = {0},
pages = {347-348},
booktitle = {Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013},
editor = {José Luis Ayala and Alex K. Jones and Patrick H. Madden and Ayse Kivilcim Coskun},
publisher = {ACM},
isbn = {978-1-4503-2032-0},
}