Clear: <u>c</u>ross-<u>l</u>ayer <u>e</u>xploration for <u>a</u>rchitecting <u>r</u>esilience combining hardware and software techniques to tolerate soft errors in processor cores

Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra. Clear: <u>c</u>ross-<u>l</u>ayer <u>e</u>xploration for <u>a</u>rchitecting <u>r</u>esilience combining hardware and software techniques to tolerate soft errors in processor cores. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016. pages 68, ACM, 2016. [doi]

@inproceedings{ChengMSCCSSLABM16,
  title = {Clear: <u>c</u>ross-<u>l</u>ayer <u>e</u>xploration for <u>a</u>rchitecting <u>r</u>esilience combining hardware and software techniques to tolerate soft errors in processor cores},
  author = {Eric Cheng and Shahrzad Mirkhani and Lukasz G. Szafaryn and Chen-Yong Cher and Hyungmin Cho and Kevin Skadron and Mircea R. Stan and Klas Lilja and Jacob A. Abraham and Pradip Bose and Subhasish Mitra},
  year = {2016},
  doi = {10.1145/2897937.2897996},
  url = {http://doi.acm.org/10.1145/2897937.2897996},
  researchr = {https://researchr.org/publication/ChengMSCCSSLABM16},
  cites = {0},
  citedby = {0},
  pages = {68},
  booktitle = {Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016},
  publisher = {ACM},
  isbn = {978-1-4503-4236-0},
}