Clear: <u>c</u>ross-<u>l</u>ayer <u>e</u>xploration for <u>a</u>rchitecting <u>r</u>esilience combining hardware and software techniques to tolerate soft errors in processor cores

Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra. Clear: <u>c</u>ross-<u>l</u>ayer <u>e</u>xploration for <u>a</u>rchitecting <u>r</u>esilience combining hardware and software techniques to tolerate soft errors in processor cores. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016. pages 68, ACM, 2016. [doi]

Abstract

Abstract is missing.