Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra. Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). IEEE Trans. on CAD of Integrated Circuits and Systems, 37(9):1839-1852, 2018. [doi]

@article{ChengMSCCSSLABM18,
  title = {Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)},
  author = {Eric Cheng and Shahrzad Mirkhani and Lukasz G. Szafaryn and Chen-Yong Cher and Hyungmin Cho and Kevin Skadron and Mircea R. Stan and Klas Lilja and Jacob A. Abraham and Pradip Bose and Subhasish Mitra},
  year = {2018},
  doi = {10.1109/TCAD.2017.2752705},
  url = {https://doi.org/10.1109/TCAD.2017.2752705},
  researchr = {https://researchr.org/publication/ChengMSCCSSLABM18},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {37},
  number = {9},
  pages = {1839-1852},
}