Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC

Yuanqing Cheng, Lei Zhang 0008, Yinhe Han, Jun Liu, Xiaowei Li 0001. Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011. pages 181-186, IEEE Computer Society, 2011. [doi]

@inproceedings{ChengZHLL11,
  title = {Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC},
  author = {Yuanqing Cheng and Lei Zhang 0008 and Yinhe Han and Jun Liu and Xiaowei Li 0001},
  year = {2011},
  doi = {10.1109/ATS.2011.40},
  url = {http://doi.ieeecomputersociety.org/10.1109/ATS.2011.40},
  researchr = {https://researchr.org/publication/ChengZHLL11},
  cites = {0},
  citedby = {0},
  pages = {181-186},
  booktitle = {Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011},
  publisher = {IEEE Computer Society},
  isbn = {978-1-4577-1984-4},
}