High speed algorithm and VLSI architecture design for decoding BCH product codes - researchr publication authors

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Zhipei Chi, Keshab K. Parhi. High speed algorithm and VLSI architecture design for decoding BCH product codes. In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2002, May 13-17 2002, Orlando, Florida, USA. pages 3089-3092, IEEE, 2002. [doi]

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