Zhipei Chi, Keshab K. Parhi. High speed algorithm and VLSI architecture design for decoding BCH product codes. In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2002, May 13-17 2002, Orlando, Florida, USA. pages 3089-3092, IEEE, 2002. [doi]
@inproceedings{ChiP02-0,
title = {High speed algorithm and VLSI architecture design for decoding BCH product codes},
author = {Zhipei Chi and Keshab K. Parhi},
year = {2002},
doi = {10.1109/ICASSP.2002.5745302},
url = {http://dx.doi.org/10.1109/ICASSP.2002.5745302},
researchr = {https://researchr.org/publication/ChiP02-0},
cites = {0},
citedby = {0},
pages = {3089-3092},
booktitle = {Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2002, May 13-17 2002, Orlando, Florida, USA},
publisher = {IEEE},
isbn = {0-7803-7402-9},
}