Zhipei Chi, Keshab K. Parhi. High speed VLSI architecture design for block turbo decoder. In ISCAS (4). pages 901-904, 2002. [doi]
@inproceedings{ChiP02,
title = {High speed VLSI architecture design for block turbo decoder},
author = {Zhipei Chi and Keshab K. Parhi},
year = {2002},
doi = {10.1109/ISCAS.2002.1009987},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2002.1009987},
tags = {architecture, design},
researchr = {https://researchr.org/publication/ChiP02},
cites = {0},
citedby = {0},
pages = {901-904},
booktitle = {ISCAS (4)},
}