A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider - researchr publication authors

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Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang. A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 3051-3054, IEEE, 2007. [doi]

This author has not been identified. Look up 'Baoyong Chi' in GoogleThis author has not been identified. Look up 'Xueyi Yu' in GoogleThis author has not been identified. Look up 'Woogeun Rhee' in GoogleThis author has not been identified. Look up 'Zhihua Wang' in Google

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