Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang. A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 3051-3054, IEEE, 2007. [doi]
@inproceedings{ChiYRW07,
title = {A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider},
author = {Baoyong Chi and Xueyi Yu and Woogeun Rhee and Zhihua Wang},
year = {2007},
doi = {10.1109/ISCAS.2007.378052},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2007.378052},
researchr = {https://researchr.org/publication/ChiYRW07},
cites = {0},
citedby = {0},
pages = {3051-3054},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA},
publisher = {IEEE},
}