Su-Jin Cho, Jae-Woo Ahn, Hyojin Choi, Wonyong Sung. Performance analysis of multi-bank DRAM with increased clock frequency. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 2477-2480, IEEE, 2012. [doi]
@inproceedings{ChoACS12,
title = {Performance analysis of multi-bank DRAM with increased clock frequency},
author = {Su-Jin Cho and Jae-Woo Ahn and Hyojin Choi and Wonyong Sung},
year = {2012},
doi = {10.1109/ISCAS.2012.6271802},
url = {http://dx.doi.org/10.1109/ISCAS.2012.6271802},
researchr = {https://researchr.org/publication/ChoACS12},
cites = {0},
citedby = {0},
pages = {2477-2480},
booktitle = {2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012},
publisher = {IEEE},
isbn = {978-1-4673-0218-0},
}