Su-Jin Cho, Jae-Woo Ahn, Hyojin Choi, Wonyong Sung. Performance analysis of multi-bank DRAM with increased clock frequency. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 2477-2480, IEEE, 2012. [doi]
Abstract is missing.