A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation - researchr publication authors

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Edward Choi, Injun Choi, Chanhee Jeon, Gichan Yun, Donghyeon Yi, Sohmyung Ha, Ik Joon Chang, Minkyu Je. A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation. In IEEE Custom Integrated Circuits Conference, CICC 2022, Newport Beach, CA, USA, April 24-27, 2022. pages 1-2, IEEE, 2022. [doi]

This author has not been identified. Look up 'Edward Choi' in GoogleThis author has not been identified. Look up 'Injun Choi' in GoogleThis author has not been identified. Look up 'Chanhee Jeon' in GoogleThis author has not been identified. Look up 'Gichan Yun' in GoogleThis author has not been identified. Look up 'Donghyeon Yi' in GoogleThis author has not been identified. Look up 'Sohmyung Ha' in GoogleThis author has not been identified. Look up 'Ik Joon Chang' in GoogleThis author has not been identified. Look up 'Minkyu Je' in Google

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