Table of Contents

• Smart Threads for Tissue-Embedded BioelectronicsSameer Sonkusale. 1-7 [doi]
• A 2.86Gb/s Fully-Flexible MU-MIMO Processor for Jointly Optimizing User Selection, Power Allocation, and Precoding in 28nm CMOS TechnologySeungsik Moon, Namyoon Lee, Youngjoo Lee. 1-2 [doi]
• A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz RangeRenze Gan, Liangjian Lyu, Geng Mu, C.-J. Richard Shi. 1-2 [doi]
• IC and Array Technologies for 100-300GHz WirelessMark J. W. Rodwell, Ahmed S. H. Ahmed, M. Seo, Utku Soylu, A. Alizadeh, Navid Hosseinzadeh. 1-5 [doi]
• The Rise of SoC FPAA DevicesJennifer Hasler. 1-8 [doi]
• A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracyYongxin Li, Nilanjan Pal, Tianyu Wang 0006, Mostafa Gamal Ahmed, Ahmed Abdelrahman, Mohamed Badr Younis, Ruhao Xia, Kyu-Sang Park, Pavan Kumar Hanumolu. 1-2 [doi]
• A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFETYuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, II-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo. 1-2 [doi]
• A Lossless and Modeling Attack-Resistant Strong PUF with <4E-8 Bit Error RateYan He, Qixuan Yu, Kaiyuan Yang 0001. 1-2 [doi]
• %-Efficiency 5-Ratio Switched-Photovoltaic DC-DC ConverterSandeep Reddy Kukunuru, Loai G. Salem. 1-2 [doi]
• Interconnect in the Era of 3DICShenggao Li, Mu-Shan Lin, Wei-Chih Chen, Chien-Chun Tsai. 1-5 [doi]
• An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization SystemsQiang Liu 0011, Zishen Wan, Bo Yu, Weizhuang Liu, Shaoshan Liu, Arijit Raychowdhury. 1-2 [doi]
• A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGAHongyu Wang, Wei Zhou, Xiangyu Zhang, Xin Lou. 1-2 [doi]
• DCT-RAM: A Driver-Free Process-In-Memory 8T SRAM Macro with Multi-Bit Charge-Domain Computation and Time-Domain QuantizationZhiYu Chen, Qing Jin, Zhanghao Yu, Yanzhi Wang, Kaiyuan Yang 0001. 1-2 [doi]
• Cryogenic CMOS for Qubit Control and ReadoutStefano Pellerano, Sushil Subramanian, Jong Seok Park, Bishnu Patra, Todor Mladenov, Xiao Xue, Lieven M. K. Vandersypen, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano. 1-8 [doi]
• System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec AvatarsH. Ekin Sumbul, Tony F. Wu, Yuecheng Li, Syed Shakib Sarwar, William Koven, Eli Murphy-Trotzky, Xingxing Cai, Elnaz Ansari, Daniel H. Morris, Huichu Liu, Doyun Kim, Edith Beigné. 1-8 [doi]
• A Review of Silicon Photonics LiDARHossein Hashemi 0001. 1-8 [doi]
• 110-GHz-Bandwidth InP-HBT AMUX/ADEMUX Circuits for Beyond-1-Tb/s/ch Digital Coherent Optical TransceiversMunehiko Nagatani, Hitoshi Wakita, Teruo Jyo, Tsutomu Takeya, Hiroshi Yamazaki, Yoshihiro Ogiso, Miwa Mutoh, Yuta Shiratori, Minoru Ida, Fukutaro Hamaoka, Masanori Nakamura, Takayuki Kobayashi, Hiroyuki Takahashi, Yutaka Miyamoto. 1-8 [doi]
• An 86.7%-Efficient Three-Level Boost Converter with Active Voltage Balancing for Thermoelectric Energy HarvestingLoan Pham-Nguyen, Nam Nguyen-Dac, Thinh Tran-Dinh, Hieu Minh Pham, Minkyu Je, Sang-Gug Lee, Hanh-Phuc Le. 1-2 [doi]
• A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy DetectionBowen Wang, Haixin Song, Woogeun Rhee, Zhihua Wang 0001. 1-2 [doi]
• A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged PhotodiodesDhruv Patel, Alireza Sharif Bakhtiar, Anthony Chan Carusone. 1-2 [doi]
• Spiking Neural Network Integrated Circuits: A Review of Trends and Future DirectionsArindam Basu, Lei Deng, Charlotte Frenkel, Xueyong Zhang. 1-8 [doi]
• A Digital Cascoded Signature Attenuation Countermeasure with Intelligent Malicious Voltage Drop Attack Detector for EM/Power SCA Resilient Parallel AES-256Archisman Ghosh, Dong-Hyun Seo, Debayan Das, Santosh Ghosh, Shreyas Sen. 1-2 [doi]
• A 19-30ppm/°C Temperature Coefficient Sub-Nanowatt CMOS Voltage Reference with 10-µA Sourcing CapabilityHongchang Qiao, Chenchang Zhan. 1-2 [doi]
• An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applicationsAvishek Biswas, Hetul Sanghvi, Mahesh Mehendale, G. Preet. 1-2 [doi]
• A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto AcceleratorArchisman Ghosh, Jose Maria Bermudo Mera, Angshuman Karmakar, Debayan Das, Santosh Ghosh, Ingrid Verbauwhede, Shreyas Sen. 1-2 [doi]
• A Phase-Modulation Phase-Shifting Phased-Array Transmitter with 10-Bit Fast-Locking Phase Self-Calibration and 0/2.5/6/12dB Power Back-Offs Efficiency EnhancementJie Zhou, Huizhen Jenny Qian, Bingzheng Yang, Yiyang Shu, Xun Luo. 1-2 [doi]
• A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit ComputationEdward Choi, Injun Choi, Chanhee Jeon, Gichan Yun, Donghyeon Yi, Sohmyung Ha, Ik Joon Chang, Minkyu Je. 1-2 [doi]
• A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFETYuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, II-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo. 1-2 [doi]
• All Rivers Flow to the Sea: A High Power Density Wireless Power Receiver with Split-Dual-Path Rectification and Hybrid-Quad-Path Step-Down ConversionZixiao Lin, Yan Lu 0002, Fangyu Mao, Chuang Wang 0004, Rui Paulo Martins. 1-2 [doi]
• A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM processJoohwan Kim, Junyoung Park, Jindo Byun, Changkyu Seol, Chang-Soo Yoon, Eunseok Shin, Hyunyoon Cho, Youngdo Um, Sucheol Lee, Hyungmin Jin, Kwangseob Shin, Hyunsub Norbert Rie, Minsu Jung, Jin-Hee Park, Go-Eun Cha, MinJae Lee, Youngmin Kim, Byeori Han, Yuseong Jeon, Jisun Lee, Hyejeong So, Sungduk Kim, Wansoo Park, Tae-young Kim, Youngdon Choi, Jung Hwan Choi, Hyungjong Ko, Sang Hyun Lee. 1-2 [doi]
• A Compact Wideband Joint Bidirectional Class-G Digital Doherty Switched-Capacitor Transmitter and N-Path Quadrature Receiver through Capacitor Bank SharingJeongseok Lee, Doohwan Jung, David Munzer, Hua Wang 0006. 1-2 [doi]
• 2 512 × 256 Multimodal CMOS Array for Spatiochemical Imaging of Bacterial BiofilmsKangping Hu, Joseph Incandela, Xiaoyu Lian, Joseph W. Larkin, Jacob K. Rosenstein. 1-2 [doi]
• Photoplethysmography (PPG) Sensor Circuit Design TechniquesQiuyang Lin, Christina Avidikou, Filip Tavernier, Nick Van Helleputte. 1-8 [doi]
• A 1-to-4GHz Multi-Mode Digital Transmitter in 40nm CMOS Supporting 200MHz 1024-QAM OFDM signals with more than 23dBm/66% Peak Power/Drain EfficiencyMohammadreza Beikmirza, Yiyu Shen, Leo C. N. de Vreede, Morteza S. Alavi. 1-2 [doi]
• 5GHz SRAM for High-Performance Compute Platform in 5nm CMOSR. Mathur, M. Kumar, Vivek Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. K. Chong. 1-2 [doi]
• A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power HarvestingZiyi Chang, Changgui Yang, Yunshan Zhang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan 0001, Bo Zhao, Yong Chen. 1-2 [doi]
• An energy-harvesting stamp-sized reader for distance-immune interrogation of passive wireless sensorsSiavash Kananian, Cheng Chen, Ada S. Y. Poon. 1-2 [doi]
• A 915-1220 TOPS/W Hybrid In-Memory Computing based Image Restoration and Region Proposal Integrated Circuit for Neuromorphic Vision Sensors in 65nm CMOSXueyong Zhang, Arindam Basu. 1-2 [doi]
• A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy DetectionBowen Wang, Cong Ding 0004, Yunzhao Nie, Woogeun Rhee, Zhihua Wang 0001. 1-2 [doi]
• A Highly-Integrated 20-300V 0.5W Active-Clamp Flyback DCDC Converter with 76.7% Peak EfficiencyChristoph Rindfleisch, Jens Otten, Bernhard Wicht. 1-2 [doi]
• A 220 GHz Sliding-IF Quadrature Transmitter With 38-dB Conversion Gain and 8-dBm Psat in 0.13-µm SiGe BiCMOSZekun Li, Jixin Chen, Jiayang Yu, Huanbo Li, Zichun Zheng, Rui Zhou, Peigen Zhou, Zhe Chen, Wei Hong 0002. 1-2 [doi]
• PVT Tolerant Zero Bit-Error-Rate Physical Unclonable Function Exploiting Hot Carrier Injection Aging in 7nm FinFET TechnologyJyothi Bhaskarr Velamala, Siang-jhih Sean Wu, Padma Penmatsa, Kuan-Yueh James Shen, David Johnston, Rachael Parker. 1-2 [doi]
• A 0.66 W/mm2 Power Density, 92.4% Peak Efficiency Hybrid Converter with nH-Scale Inductors for 12 V SystemTianshi Xie, Jianglin Zhu, Tom Byrd, Dragan Maksimovic, Hanh-Phuc Le. 1-2 [doi]
• TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency AdaptionJieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jun Yang, Mingoo Seok. 1-2 [doi]
• StreamGCN: Accelerating Graph Convolutional Networks with Streaming ProcessingAtefeh Sohrabizadeh, Yuze Chi, Jason Cong. 1-8 [doi]
• Switched-Capacitor CircuitsDavid J. Allstot, Un-Ku Moon, Gabor C. Temes. 1-8 [doi]
• Review, Survey, and Benchmark of Recent Digital LDO Voltage RegulatorsZhaoqing Wang, Sung J. Kim, Keith A. Bowman, Mingoo Seok. 1-8 [doi]
• An Energy-Efficient Cardiac Arrhythmia Classification Processor using Heartbeat Difference based Classification and Event-Driven Neural Network Computation with Adaptive Wake-UpJ. Liu, J. Xiao, J. Fan, Q. Liu, Z. Zhu, S. Li, Z. Zhang, S. Yang, W. Shan, S. Lin, L. Chang, L. Zhou, J. Zhou. 1-2 [doi]
• System technology co-optimization and design challenges for 3D ICSupreet Jeloka, Brian Cline, Shidhartha Das, Benoit Labbe, Alejandro Rico, Rainer Herberholz, Javier A. DeLaCruz, Rahul Mathur, Shawn Hung. 1-6 [doi]
• A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise SuppressionYangtao Dong, Chirn Chye Boon, Kaituo Yang, Zhe Liu. 1-2 [doi]
• A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation SchemeHao Zhang, Linxiao Shen, Shichuang Zhang, Heyi Li, Yihan Zhang, Zhichao Tan, Ru Huang, Le Ye. 1-2 [doi]
• A 181µW Real-Time 3-D Hand Gesture Recognition System based on Bi-directional Convolution and Computing-Efficient Feature ClusteringYuncheng Lu, Zehao Li, Yuzong Chen, Tony Tae-Hyoung Kim. 1-2 [doi]
• A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizingMingqiang Guo, Sai-Weng Sin, Liang Qi, Gang Xiao 0001, Rui Paulo Martins. 1-2 [doi]
• A 10/2.5-Gb/s Hyper-Supplied CMOS Low-Noise Burst-Mode TIA with Loud Burst Protection and Gearbox Automatic Offset Cancellation for XGS-PONChen Tan, Wei Huang, Yonghui Fan, Jing Li, Chuanhao Yu, Wenbo Shi, Shiti Huang, Zhenyu Yin, Chenfan Cao, Lei Jing, Zhixiong Ren, Xiaoyan Gui, Bing Zhang, Dan Li, Li Geng. 1-2 [doi]
• Watt-Level Triple-Mode Quadrature SFCPA with 56 Peaks for Ultra-Deep PBO Efficiency Enhancement Using IQ Intrinsic Interaction and Adaptive Phase CompensationBingzheng Yang, Huizhen Jenny Qian, Yiyang Shu, Jie Zhou, Xun Luo. 1-2 [doi]
• MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and MitigationChuxiong Lin, Weifeng He, Yannan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok. 1-2 [doi]
• A 48dB-SFDR, 43dB-SNDR, 50GS/s 9-bit 2x-interleaved Nyquist DAC in Intel 16Hariprasad Chandrakumar, Thomas W. Brown, Dimitri Frolov, Zinia Tuli, Iwen Huang, Said Rami. 1-2 [doi]
• Design Techniques for High Linearity and Dynamic Range Digital to Analog ConvertersAyman Shabra, Yun-Shiang Shu, Shon-Hang Wen, Kuan-Dar Chen. 1-8 [doi]
• T-PIM: A 2.21-to-161.08TOPS/W Processing-In-Memory Accelerator for End-to-End On-Device TrainingJaehoon Heo, Junsoo Kim, Wontak Han, Sukbin Lim, Joo-Young Kim. 1-2 [doi]
• High-Speed Digital-to-Analog Converter Design Towards High Dynamic RangeShiyu Su, Mike Shuo-Wei Chen. 1-8 [doi]
• Piezoelectric-Based Power Conversion: Recent Progress, Opportunities, and ChallengesJessica D. Boles, Joshua J. Piel, Ng Elaine, Joseph E. Bonavia, Jeffrey H. Lang, David J. Perreault. 1-8 [doi]
• A 400-to-12 V Fully Integrated Switched-Capacitor DC-DC Converter Achieving 119 mW/mm2 at 63.6 % EfficiencyTuur Van Daele, Filip Tavernier. 1-2 [doi]
• A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost OperationDonghee Cho, Hyungjoo Cho, Sein Oh, Yoontae Jung, Sohmyung Ha, Chul Kim, Minkyu Je. 1-2 [doi]
• nd-order Vector-Quantizer DEMWei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun. 1-2 [doi]
• A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked NeurostimulationUisub Shin, Cong Ding 0014, Laxmeesha Somappa, Virginia Woods, Alik S. Widge, Mahsa Shoaran. 1-2 [doi]
• A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR InductorWoojoong Jung, Minsu Kim, Hyunjun Park, Sungmin Yoo, Tae-Hwang Kong, Jun Hyeok Yang, Michael Choi, Jongshin Shin, Hyung-Min Lee. 1-2 [doi]
• An 0.92 mJ/frame High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient CacheZhiyong Li, Sangjin Kim, Dongseok Im, Donghyeon Han, Hoi-Jun Yoo. 1-2 [doi]
• A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural NetworksBo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok. 1-2 [doi]
• A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency QuadruplerFrancesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Lesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. 1-2 [doi]
• A 23-37GHz Autonomous Two-Dimensional MIMO Receiver Array with Rapid Full-FoV Spatial Filtering for Unknown Interference SuppressionBoce Lin, Tzu-Yuan Huang, Amr Ahmed, Min-Yu Huang, Hua Wang 0006. 1-2 [doi]
• A 1.8GΩ-Input-Impedance 0.15µV-Input-Referred-Ripple Chopper Amplifier with Local Positive Feedback and SAR-Assisted Ripple ReductionTianxiang Qu, Qinjing Pan, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu 0001. 1-2 [doi]
• An Up to 10MHz 6.8% Minimum Duty Ratio GaN Driver with Dual-MOS-Switches Bootstrap and Adaptive Short-Pulse Based High-CMTI Level Shifter Achieving 6.05% Efficiency ImprovementXin-ming, Zhiyi Lin, Tian-yi Sun, Yao Qin, Yuan-yuan Liu, Chun-wang Zhuang, Zhao-ji Li, Bo Zhang 0027. 1-2 [doi]
• A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOSMarcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, Friedel Gerfers. 1-2 [doi]
• 22-30GHz Quadrature Hybrid SCPA with LO Leakage Self-Suppression and Distributed Parasitic-Cancelling Sub-PA Array for Linearity and Efficiency EnhancementBingzheng Yang, Huizhen Jenny Qian, Yiyang Shu, Jie Zhou, Xun Luo. 1-2 [doi]
• Hardware/software Co-design for Neuromorphic SystemsRajit Manohar. 1-5 [doi]
• Wireless Frequency-Division Multiplexed 3D Magnetic Localization for Low Power Sub-mm Precision Capsule EndoscopyMichella Rustom, Constantine Sideris. 1-2 [doi]
• An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization ProblemsMuya Chang, Xunzhao Yin, Zoltán Toroczkai, Xiaobo Hu 0001, Arijit Raychowdhury. 1-2 [doi]
• Randomized Switching SAR (RS-SAR) ADC Protections for Power and Electromagnetic Side Channel SecurityMaitreyi Ashok, Edlyn V. Levine, Anantha P. Chandrakasan. 1-2 [doi]
• A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power ConditionYijie Wei, Xi Chen, Jie Gu 0001. 1-2 [doi]
• A 6.8µW AFE for Ear EEG Recording with Simultaneous Impedance Measurement for Motion Artifact CancellationAviral Pandey, Sina Faraji Alamouti, Justin Doong, Ryan Kaveh, Cem Yalcin, Mohammad Meraj Ghanbari, Rikky Muller. 1-2 [doi]
• A 2GHz voltage mode power scalable RF-Front-End with 2.5dB-NF and 0.5dBm-1dBCPJustin Yonghui Kim, Antonio Liscidini. 1-2 [doi]
• A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOSRuichang Ma, Haikun Jia, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi. 1-2 [doi]
• A Fully In-Package 4-Phase Fixed-Frequency DAB Hysteretic Controlled DC-DC Converter with Enhanced Efficiency, Load Regulation and Transient ResponseLei Zhao, Junyao Tang, Cheng Huang. 1-2 [doi]
• A SAR-Assisted DC-Coupled Chopper-Stabilized 20μs-Artifact-Recovery $\Delta \Sigma$ ADC for Simultaneous Neural Recording and StimulationTania Moeinfard, Georg Zoidl, Hossein Kassiri. 1-2 [doi]
• A 0.8V/0.6V 2.2μW Time-Domain Analog Front-End with $540\text{mV}_{\text{pp}}$ Input Range, 81.6dB SNDR and $80\mathrm{M}\Omega$ Input ImpedanceLiheng Liu, Tianxiang Qu, Pengjie Wang, Yao Zhang, Zhiliang Hong, Jiawei Xu 0001. 1-2 [doi]
• DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nmAnimesh Gupta, Viveka Konandur Rajanna, Thoithoi Salam, Saurabh Jain, Orazio Aiello, Paolo Crovetti, Massimo Alioto. 1-2 [doi]
• A $36\times 40$ Wireless Fluorescence Image Sensor for Real-Time Microscopy in Cancer TherapyRozhan Rabbani, Hossein Najafiaghdam, Biqi Zhao, Megan Zeng, Vladimir Stojanovic, Rikky Muller, Mekhail Anwar. 1-2 [doi]
• A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System with Level-Adaptive Duty Modulation and Offset Charge Balancing for Muscular StimulationKyeongho Eom, Han-Sol Lee, Minju Park, Hyung-Min Lee, Seung-Min Yang, Jong Chan Choe, Suk-Won Hwang, Young-Woo Suh. 1-2 [doi]
• Wireless, Batteryless, and Secure Implantable System-on-a-Chip for 1.37mmHg Strain Sensing with Bandwidth Reconfigurability for Cross-Tissue AdaptationMohamed R. Abdelhamid, U. Ha, Utsav Banerjee, Fadel Adib, Anantha P. Chandrakasan. 1-2 [doi]
• A Calibration-Free 13b 625MS/s Tri-State Pipelined-SAR ADC with PVT-Insensitive Inverter-Based Residue AmplifierXiaofeng Guo, Run Chen, Rongfeng Xu, Bin Li, Zhenqi Chen. 1-2 [doi]
• ULP Receivers in Self-Powered Industrial loT Applications: Challenges and ProspectsKuo-Ken Huang, Jonathan K. Brown, Richard K. Sawyer, Christopher J. Lukas, Farah B. Yahya, Alice Wang, Nathan E. Roberts, Benton H. Calhoun, David D. Wentzloff. 1-8 [doi]
• A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NRZhixian Deng, Huizhen Jenny Qian, Changxuan Han, Yifan Li, Xun Luo. 1-2 [doi]
• Filtering Trans-Impedance Amplifiers: from mW of Power to GHz of BandwidthNimesh Nadishka Miral, Karan Sohal, Danilo Manstretta, Rinaldo Castello. 1-8 [doi]
• Recent Advances in High-Performance Frequency Synthesizer DesignSalvatore Levantino. 1-7 [doi]
• Comprehending In-memory Computing Trends via Proper BenchmarkingNaresh R. Shanbhag, Saion K. Roy. 1-7 [doi]
• 3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by TechnologyTaejoong Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, Woojin Rim, Sanghoon Baek, Sangyeop Baeck, Jonghoon Jung. 1-7 [doi]
• Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128x128 SPAD Receiver with SNR-Based Pixel Binning and Resolution UpscalingShenglong Zhuo, Lei Zhao, Tao Xia, Lei Wang, Shi Shi, Yifan Wu, Chang Liu, Chill Wang, Yuwei Wang, Yuan Li, Hengwei Yu, Jiqing Xu, Aaron Wang, Zhihong Lin, Yun Chen, Rui Bai, XueFeng Chen, Patrick Yin Chiang. 1-2 [doi]
• A 0.5-3GHz Receiver with a Parallel Preselect Filter Achieving 120dB/dec Channel Selectivity and +28dBm Out-of-Band IIP3Muhammad Ali Montazerolghaem, Leo C. N. de Vreede, Masoud Babaie. 11-12 [doi]