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Bum-Hee Choi, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang. A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's. IEICE Electronic Express, 13(24):20161086, 2016. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A low jitter burst-mode clock and data recovery circuit with two symmetric VCO'sBum-Hee Choi, Kyung-Sub Son, Jin-Ku Kang. apccas 2016: 344-347 [doi] A New 1.25-Gb/s Burst Mode Clock and Data Recovery Circuit Using Two Digital Phase Aligners and a Phase InterpolatorChang-Kyung Seong, Seung Woo Lee, Woo-Young Choi. ieicet, 91-B(5):1397-1402, 2008. [doi] A CMOS clock and data recovery with two-XOR phase-frequency detector circuitJin-Ku Kang, Dong-Hee Kim. iscas 2001: 266-269 [doi]
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