Rituparna Choudhury, P. Rangababu. Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder. In Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh, editors, VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers. Volume 711 of Communications in Computer and Information Science, pages 742-750, Springer, 2017. [doi]
@inproceedings{ChoudhuryR17-0,
title = {Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder},
author = {Rituparna Choudhury and P. Rangababu},
year = {2017},
doi = {10.1007/978-981-10-7470-7_70},
url = {https://doi.org/10.1007/978-981-10-7470-7_70},
researchr = {https://researchr.org/publication/ChoudhuryR17-0},
cites = {0},
citedby = {0},
pages = {742-750},
booktitle = {VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
editor = {Brajesh Kumar Kaushik and Sudeb Dasgupta and Virendra Singh},
volume = {711},
series = {Communications in Computer and Information Science},
publisher = {Springer},
isbn = {978-981-10-7470-7},
}