Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm

Nasirul Chowdhury, Jeff Wight, Christopher Mozak, Nasser A. Kurd. Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm. In Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, April 23-25, 2012. pages 1-4, IEEE, 2012. [doi]

Authors

Nasirul Chowdhury

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Jeff Wight

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Christopher Mozak

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Nasser A. Kurd

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