Zhufei Chu, Yinshui Xia, Lun-Yao Wang. Level shifter planning for timing constrained multi-voltage SoC floorplanning. In Joseph R. Cavallaro, Tong Zhang 0002, Alex K. Jones, Hai Helen Li, editors, Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014. pages 329-334, ACM, 2014. [doi]
@inproceedings{ChuXW14,
title = {Level shifter planning for timing constrained multi-voltage SoC floorplanning},
author = {Zhufei Chu and Yinshui Xia and Lun-Yao Wang},
year = {2014},
doi = {10.1145/2591513.2591587},
url = {http://doi.acm.org/10.1145/2591513.2591587},
researchr = {https://researchr.org/publication/ChuXW14},
cites = {0},
citedby = {0},
pages = {329-334},
booktitle = {Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014},
editor = {Joseph R. Cavallaro and Tong Zhang 0002 and Alex K. Jones and Hai Helen Li},
publisher = {ACM},
isbn = {978-1-4503-2816-6},
}