Abstract is missing.
- VLSI systems for neurocomputing and health informaticsKeshab K. Parhi. 1-2 [doi]
- Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesisMatheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans. 3-8 [doi]
- System-level reliability exploration framework for heterogeneous MPSoCZheng Wang, Chao Chen, Piyush Sharma, Anupam Chattopadhyay. 9-14 [doi]
- A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustnessRickard Ewetz, Anirudh Udupa, Ganesh Subbarayan, Cheng-Kok Koh. 15-20 [doi]
- A feasibility study on robust programmable delay element design based on neuron-MOS mechanismRenyuan Zhang, Mineo Kaneko. 21-26 [doi]
- Horizontal benchmark extension for improved assessment of physical CAD researchAndrew B. Kahng, Hyein Lee, Jiajia Li. 27-32 [doi]
- OCV-aware top-level clock tree optimizationTuck Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath. 33-38 [doi]
- Modeling of the charging behavior of li-ion batteries based on manufacturer's dataAlessandro Sassone, Donghwa Shin, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino. 39-44 [doi]
- High level energy modeling of controller logic in data cachesPreeti Ranjan Panda, Sourav Roy, Srikanth Chandrasekaran, Namita Sharma, Jasleen Kaur, Sarath Kumar Kandalam, Nagaraj N.. 45-50 [doi]
- 3D-SWIFT: a high-performance 3D-stacked wide IO DRAMTao Zhang, Cong Xu, Ke Chen, Guangyu Sun, Yuan Xie. 51-56 [doi]
- Minimum implant area-aware gate sizing and placementAndrew B. Kahng, Hyein Lee. 57-62 [doi]
- A multi-stage leakage aware resource management technique for reconfigurable architecturesPham Nam Khanh, Amit Kumar Singh, Akash Kumar. 63-68 [doi]
- A performance enhancing hybrid locally mesh globally star NoC topologyTuhin Subhra Das, Prasun Ghosal, Saraju P. Mohanty, Elias Kougianos. 69-70 [doi]
- VLSI implementation of linear MIMO detection with boosted communications performance: extended abstractDominik Auras, Dominik Rieth, Rainer Leupers, Gerd Ascheid. 71-72 [doi]
- Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate controlYue Fu, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram. 73-74 [doi]
- A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC convertersJing Lu, Yong-Bin Kim. 75-76 [doi]
- WeDBless: weighted deflection bufferless router for mesh NoCsSimi Zerine Sleeba, John Jose, Mini M. G.. 77-78 [doi]
- Trade-off between energy and quality of service through dynamic operand truncation and fusionWenchao Qian, Robert Karam, Swarup Bhunia. 79-80 [doi]
- A novel low-power and in-place split-radix FFT processorZhuo Qian, Martin Margala. 81-82 [doi]
- H.264 8x8 inverse transform architecture optimizationFabio Pereira, André Borin Soarez, Altamiro Amadeu Susin, Alexsandro Cristovão Bonatto, Marcelo Negreiros. 83-84 [doi]
- Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennasMd Shahriar Shamim, Naseef Mansoor, Aman Samaiyar, Amlan Ganguly, Sujay Deb, Shobha Sunndar Ram. 85-86 [doi]
- Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memoryMichael Gautschi, Davide Rossi, Luca Benini. 87-88 [doi]
- Performance modeling of virtualized custom logic computationsMichael J. Hall, Roger D. Chamberlain. 89-90 [doi]
- Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract]Mineo Kaneko. 91-92 [doi]
- An area efficient low power high speed S-Box implementation using power-gated PLAHo-Joon Lee, Yong-Bin Kim. 93-94 [doi]
- FPGA based implementation of a genetic algorithm for ARMA model parameters identificationHocine Merabti, Daniel Massicotte. 95-96 [doi]
- Highly adaptive and congestion-aware routing for 3D NoCsManoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Seok-Bum Ko, Mark Zwolinski. 97-98 [doi]
- Adaptive compressive sensing for low power wireless sensorsAdam Watkins, Venkata Naresh Mudhireddy, Haibo Wang, Spyros Tragoudas. 99-104 [doi]
- Regulator-gating: adaptive management of on-chip voltage regulatorsSelçuk Köse. 105-110 [doi]
- Logic block and design methodology for via-configurable structured ASIC using dual supply voltagesTa-Kai Lin, Kuen-Wey Lin, Chang-Hao Chiu, Rung-Bin Lin. 111-116 [doi]
- Squash: a scalable quantum mapper considering ancilla sharingMohammad Javad Dousti, Alireza Shafaei, Massoud Pedram. 117-122 [doi]
- Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memoryKenneth Ramclam, Swaroop Ghosh. 123-128 [doi]
- A study on the use of parallel wiring techniques for sub-20nm designsRickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh. 129-134 [doi]
- Create, then innovateGene A. Frantz. 135-136 [doi]
- Smart nodes of internet of things (IoT): a hardware perspective view & implementationEdgar Sánchez-Sinencio. 137-138 [doi]
- WriteSmoothing: improving lifetime of non-volatile caches using intra-set wear-levelingSparsh Mittal, Jeffrey S. Vetter, Dong Li. 139-144 [doi]
- Reliability-aware cross-point resistive memory designCong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie. 145-150 [doi]
- Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systemsNikolaos Papandreou, Thomas P. Parnell, Haralampos Pozidis, Thomas Mittelholzer, Evangelos Eleftheriou, Charles Camp, Thomas Griffin, Gary Tressler, Andrew Walls. 151-156 [doi]
- A new methodology for reduced cost of resilienceAndrew B. Kahng, Seokhyeong Kang, Jiajia Li. 157-162 [doi]
- A hybrid framework for application allocation and scheduling in multicore systems with energy harvestingYi Xiang, Sudeep Pasricha. 163-168 [doi]
- Neural network-based accelerators for transcendental function approximationSchuyler Eldridge, Florian Raudies, David Zou, Ajay Joshi. 169-174 [doi]
- Efficient parallel beamforming for 3D ultrasound imagingPirmin Vogel, Andrea Bartolini, Luca Benini. 175-180 [doi]
- A task-oriented vision systemYang Xiao, Kevin M. Irick, Jack Sampson, Vijaykrishnan Narayanan, Chuanjun Zhang. 181-186 [doi]
- A new DRAM architecture and its control method for the system power consumptionYoshiro Riho, Kazuo Nakazato. 187-192 [doi]
- A memory mapping approach based on network customization to design conflict-free parallel hardware architecturesSaeed Ur Reehman, Cyrille Chavet, Philippe Coussy. 193-198 [doi]
- New 4T-based DRAM cell designsWei Wei, Kazuteru Namba, Fabrizio Lombardi. 199-204 [doi]
- MB-FICA: multi-bit fault injection and coverage analysisChen Jiang, Mojing Liu, Brett H. Meyer. 205-210 [doi]
- On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chipWei Song 0002, Guangda Zhang, Jim D. Garside. 211-216 [doi]
- A novel parallel adaptation of an implicit path delay grading methodJoseph Lenox, Spyros Tragoudas. 217-222 [doi]
- Simscape design flow for memristor based programmable oscillatorsEbubechukwu Agu, Saraju P. Mohanty, Elias Kougianos, Mahesh Gautam. 223-224 [doi]
- Securely outsourcing power grid simulation on cloudNaval Gupte, Jia Wang. 225-226 [doi]
- An automated design approach to map applications on CGRAsThomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin Martin, Philippe Coussy. 229-230 [doi]
- He-P2012: architectural heterogeneity exploration on a scalable many-core platformFrancesco Conti, Chuck Pilkington, Andrea Marongiu, Luca Benini. 231-232 [doi]
- On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yieldTak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu. 233-234 [doi]
- Transient analysis of gate inside junctionless transistor (GI-JLT)Pankaj Kumar, Pravin Kondekar, Sangeeta Singh. 235-236 [doi]
- Built-in generation of functional broadside tests considering primary input constraintsBo Yao, Irith Pomeranz, Srikanth Venkataraman, Enamul Amyeen. 237-238 [doi]
- TSV power supply array electromigration lifetime analysis in 3D ICSQiaosha Zou, Tao Zhang, Cong Xu, Yuan Xie. 239-240 [doi]
- A current-mode CMOS/memristor hybrid implementation of an extreme learning machineCory E. Merkel, Dhireesha Kudithipudi. 241-242 [doi]
- Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memoriesMatthias Hartmann, Halil Kükner, Prashant Agrawal, Praveen Raghavan, Liesbet Van der Perre, Wim Dehaene. 243-244 [doi]
- A design flow for physical synthesis of digital cells with ASTRANAdriel Ziesemer, Ricardo Reis, Matheus T. Moreira, Michel E. Arendt, Ney Laert Vilar Calazans. 245-246 [doi]
- A semi-formal approach for analog circuits behavioral properties verificationOns Lahiouel, Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar. 247-248 [doi]
- Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processorsAdarsh Reddy Ashammagari, Hamid Mahmoodi, Tinoosh Mohsenin, Houman Homayoun. 249-254 [doi]
- A generic implementation of a quantified predictor on FPGAsGervin Thomas, Ahmed Elhossini, Ben H. H. Juurlink. 255-260 [doi]
- A dual-rail LUT for reconfigurable logic using null convention logicJing Yu, Paul Beckett. 261-266 [doi]
- A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chipMarta Ortín-Obón, Luca Ramini, Hervé Tatenguem Fankem, Víctor Viñals, Davide Bertozzi. 267-272 [doi]
- A design approach to automatically generate on-chip monitors during high-level synthesis of hardware acceleratorMohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec. 273-278 [doi]
- Thermal-aware phase-based tuning of embedded systemsTosiron Adegbija, Ann Gordon-Ross. 279-284 [doi]
- EDA for extreme scale systems: design abstractions, metrics, and benchmarksAlex K. Jones. 285-286 [doi]
- Hardware trojan attacks in FPGA devices: threat analysis and effective counter measuresSanchita Mal-Sarkar, Aswin Raghav Krishna, Anandaroop Ghosh, Swarup Bhunia. 287-292 [doi]
- Forward-scaling, serially equivalent parallelism for FPGA placementChristian Fobel, Gary William Grewal, Deborah Stacey. 293-298 [doi]
- A parallel and reconfigurable architecture for efficient OMP compressive sensing reconstructionAmey M. Kulkarni, Houman Homayoun, Tinoosh Mohsenin. 299-304 [doi]
- Generation of reduced analog circuit models using transient simulation tracesPaul Winkler, Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar. 305-310 [doi]
- A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceiversYongsuk Choi, Yong-Bin Kim. 311-316 [doi]
- A qualitative simulation approach for verifying PLL locking propertyIbtissem Seghaier, Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar. 317-322 [doi]
- Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power railsYanzhi Wang, Xue Lin, Massoud Pedram. 323-328 [doi]
- Level shifter planning for timing constrained multi-voltage SoC floorplanningZhufei Chu, Yinshui Xia, Lun-Yao Wang. 329-334 [doi]
- Exploiting heterogeneity in MPSoCs to prevent potential trojan propagation across malicious IPsChen Liu, Chengmo Yang. 335-340 [doi]
- Optically reconfigurable gate array with an angle-multiplexed holographic memoryRetsu Moriwaki, Hikaru Maekawa, Akifumi Ogiwara, Minoru Watanabe. 341-346 [doi]
- Variability-aware design of double gate FinFET-based current mirrorsDhruva Ghai, Saraju P. Mohanty, Garima Thakral, Oghenekarho Okobiah. 347-352 [doi]
- A comparison of FinFET based FPGA LUT designsMonther Abusultan, Sunil P. Khatri. 353-358 [doi]