Zhufei Chu, Yinshui Xia, Lun-Yao Wang. Level shifter planning for timing constrained multi-voltage SoC floorplanning. In Joseph R. Cavallaro, Tong Zhang 0002, Alex K. Jones, Hai Helen Li, editors, Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014. pages 329-334, ACM, 2014. [doi]
Abstract is missing.