Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits - researchr publication authors

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Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim. Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. In 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA. pages 153-158, IEEE Computer Society, 2003. [doi]

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