Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim. Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. In 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA. pages 153-158, IEEE Computer Society, 2003. [doi]
@inproceedings{ChuangJPK03,
title = {Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits},
author = {Ching-Te Chuang and Rajiv V. Joshi and Ruchir Puri and Keunwoo Kim},
year = {2003},
url = {http://csdl.computer.org/comp/proceedings/isqed/2003/1881/00/18810153abs.htm},
tags = {design},
researchr = {https://researchr.org/publication/ChuangJPK03},
cites = {0},
citedby = {0},
pages = {153-158},
booktitle = {4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-1881-8},
}