Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj. A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. In Michael R. Lightner, Jochen A. G. Jess, editors, Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993. pages 220-223, IEEE Computer Society, 1993. [doi]
Abstract is missing.