A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS

Yung-Hui Chung, Wei-Shu Rih. A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS. In International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017. pages 216-217, IEEE, 2017. [doi]

@inproceedings{ChungR17,
  title = {A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS},
  author = {Yung-Hui Chung and Wei-Shu Rih},
  year = {2017},
  doi = {10.1109/ISOCC.2017.8368860},
  url = {https://doi.org/10.1109/ISOCC.2017.8368860},
  researchr = {https://researchr.org/publication/ChungR17},
  cites = {0},
  citedby = {0},
  pages = {216-217},
  booktitle = {International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017},
  publisher = {IEEE},
  isbn = {978-1-5386-2285-8},
}