A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology

Ching-Che Chung, Duo Sheng, Chia-Lin Chang. A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology. IEICE Electronic Express, 8(7):518-524, 2011. [doi]

Abstract

Abstract is missing.