Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo. Logic gates dynamic modeling by means of an ultra-compact MOS model. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 3250-3253, IEEE, 2012. [doi]
@inproceedings{ConsoliGP12, title = {Logic gates dynamic modeling by means of an ultra-compact MOS model}, author = {Elio Consoli and Gianluca Giustolisi and Gaetano Palumbo}, year = {2012}, doi = {10.1109/ISCAS.2012.6272018}, url = {http://dx.doi.org/10.1109/ISCAS.2012.6272018}, researchr = {https://researchr.org/publication/ConsoliGP12}, cites = {0}, citedby = {0}, pages = {3250-3253}, booktitle = {2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012}, publisher = {IEEE}, isbn = {978-1-4673-0218-0}, }