Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo. Logic gates dynamic modeling by means of an ultra-compact MOS model. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 3250-3253, IEEE, 2012. [doi]
Abstract is missing.