A Design-flow for implementing, validating and evaluating Machine-learning Classifiers on FPGAs

Jan Cordes, Maher Fakih. A Design-flow for implementing, validating and evaluating Machine-learning Classifiers on FPGAs. In Farshad Firouzi, Krishnendu Chakrabarty, Bahar Farahani, Fangming Ye, Vasilis F. Pavlidis, editors, Proceedings of the International Conference on Omni-Layer Intelligent Systems, COINS 2019, Crete, Greece, May 5-7, 2019. pages 86-91, ACM, 2019. [doi]

@inproceedings{CordesF19,
  title = {A Design-flow for implementing, validating and evaluating Machine-learning Classifiers on FPGAs},
  author = {Jan Cordes and Maher Fakih},
  year = {2019},
  doi = {10.1145/3312614.3312635},
  url = {https://doi.org/10.1145/3312614.3312635},
  researchr = {https://researchr.org/publication/CordesF19},
  cites = {0},
  citedby = {0},
  pages = {86-91},
  booktitle = {Proceedings of the International Conference on Omni-Layer Intelligent Systems, COINS 2019, Crete, Greece, May 5-7, 2019},
  editor = {Farshad Firouzi and Krishnendu Chakrabarty and Bahar Farahani and Fangming Ye and Vasilis F. Pavlidis},
  publisher = {ACM},
  isbn = {978-1-4503-6640-3},
}