VLSI Implementation of a Low-Power High-Speed Self-Timed Adder

Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo. VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. In Dimitrios Soudris, Peter Pirsch, Erich Barke, editors, Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings. Volume 1918 of Lecture Notes in Computer Science, pages 195-204, Springer, 2000. [doi]

Abstract

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