A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories

Enrico Costenaro, Massimo Violante, Dan Alexandrescu. A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. In 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece. pages 49-54, IEEE, 2011. [doi]

@inproceedings{CostenaroVA11,
  title = {A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories},
  author = {Enrico Costenaro and Massimo Violante and Dan Alexandrescu},
  year = {2011},
  doi = {10.1109/IOLTS.2011.5993810},
  url = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2011.5993810},
  tags = {rule-based},
  researchr = {https://researchr.org/publication/CostenaroVA11},
  cites = {0},
  citedby = {0},
  pages = {49-54},
  booktitle = {17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece},
  publisher = {IEEE},
  isbn = {978-1-4577-1053-7},
}