Olivier Coudert. Gate sizing for constrained delay/power/area optimization. IEEE Trans. VLSI Syst., 5(4):465-472, 1997. [doi]
@article{Coudert97:0,
title = {Gate sizing for constrained delay/power/area optimization},
author = {Olivier Coudert},
year = {1997},
doi = {10.1109/92.645073},
url = {http://doi.ieeecomputersociety.org/10.1109/92.645073},
tags = {optimization},
researchr = {https://researchr.org/publication/Coudert97%3A0},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {5},
number = {4},
pages = {465-472},
}