A 32-bit GaAs IEEE floating point multiplier using Trailing-1 s rounding algorithm - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

S. Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian. A 32-bit GaAs IEEE floating point multiplier using Trailing-1 s rounding algorithm. In Lakhmi C. Jain, editor, Electronic Technology Directions to the Year 2000, May 23-25, 1995, Adelaide, Australia, Proceedings. pages 246-252, IEEE Computer Society, 1995. [doi]

This author has not been identified. Look up 'S. Cui' in GoogleThis author has not been identified. Look up 'Neil Burgess' in GoogleThis author has not been identified. Look up 'Michael J. Liebelt' in GoogleThis author has not been identified. Look up 'Kamran Eshraghian' in Google

runs on WebDSL