A 32-bit GaAs IEEE floating point multiplier using Trailing-1 s rounding algorithm

S. Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian. A 32-bit GaAs IEEE floating point multiplier using Trailing-1 s rounding algorithm. In Lakhmi C. Jain, editor, Electronic Technology Directions to the Year 2000, May 23-25, 1995, Adelaide, Australia, Proceedings. pages 246-252, IEEE Computer Society, 1995. [doi]

@inproceedings{CuiBLE95:0,
  title = {A 32-bit GaAs IEEE floating point multiplier using Trailing-1 s rounding algorithm},
  author = {S. Cui and Neil Burgess and Michael J. Liebelt and Kamran Eshraghian},
  year = {1995},
  doi = {10.1109/ETD.1995.403466},
  url = {http://dx.doi.org/10.1109/ETD.1995.403466},
  researchr = {https://researchr.org/publication/CuiBLE95%3A0},
  cites = {0},
  citedby = {0},
  pages = {246-252},
  booktitle = {Electronic Technology Directions to the Year 2000, May 23-25, 1995, Adelaide, Australia, Proceedings},
  editor = {Lakhmi C. Jain},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-7085-1},
}