Dariusz Czysz, Janusz Rajski, Jerzy Tyszer. Low power test application with selective compaction in VLSI designs. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012. pages 1-10, IEEE Computer Society, 2012. [doi]
@inproceedings{CzyszRT12,
title = {Low power test application with selective compaction in VLSI designs},
author = {Dariusz Czysz and Janusz Rajski and Jerzy Tyszer},
year = {2012},
doi = {10.1109/TEST.2012.6401532},
url = {http://doi.ieeecomputersociety.org/10.1109/TEST.2012.6401532},
researchr = {https://researchr.org/publication/CzyszRT12},
cites = {0},
citedby = {0},
pages = {1-10},
booktitle = {2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012},
publisher = {IEEE Computer Society},
isbn = {978-1-4673-1594-4},
}