Low power test application with selective compaction in VLSI designs

Dariusz Czysz, Janusz Rajski, Jerzy Tyszer. Low power test application with selective compaction in VLSI designs. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012. pages 1-10, IEEE Computer Society, 2012. [doi]

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