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Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System

Preyesh Dalmia, Vikas, Abhinav Parashar, Akshi Tomar, Neeta Pandey. Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System. In 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018. pages 289-294, IEEE Computer Society, 2018. [doi]

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