A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS

Nicola Da Dalt, Christoph Sandner. A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS. J. Solid-State Circuits, 38(7):1275-1278, 2003. [doi]

Abstract

Abstract is missing.