Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas. Delay Analysis for Current Mode Threshold Logic Gate Designs. IEEE Trans. VLSI Syst., 25(3):1063-1071, 2017. [doi]
@article{DaraHT17,
title = {Delay Analysis for Current Mode Threshold Logic Gate Designs},
author = {Chandra Babu Dara and Themistoklis Haniotakis and Spyros Tragoudas},
year = {2017},
doi = {10.1109/TVLSI.2016.2608953},
url = {http://dx.doi.org/10.1109/TVLSI.2016.2608953},
researchr = {https://researchr.org/publication/DaraHT17},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {25},
number = {3},
pages = {1063-1071},
}