Isuru Daulagala, Ioannis Savidis. Clock tree synthesis for heterogeneous 3-D integrated circuits. In ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, SLIP 2017, Austin, TX, USA, June 17, 2017. pages 1-6, IEEE, 2017. [doi]
@inproceedings{DaulagalaS17,
title = {Clock tree synthesis for heterogeneous 3-D integrated circuits},
author = {Isuru Daulagala and Ioannis Savidis},
year = {2017},
doi = {10.1109/SLIP.2017.7974911},
url = {https://doi.org/10.1109/SLIP.2017.7974911},
researchr = {https://researchr.org/publication/DaulagalaS17},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, SLIP 2017, Austin, TX, USA, June 17, 2017},
publisher = {IEEE},
isbn = {978-1-5386-1536-2},
}